1. Technical Field
One or more embodiments of the present invention generally relate to semiconductor design. In particular, certain embodiments relate to the programming of semiconductor dies.
2. Discussion
Modern day computer systems have various circuit boards with sockets designed to receive computing components such as processor integrated circuit (IC) chips, memory chips, etc. A memory chip and/or a processor IC chip may include various types of memory, such as read-only memory (ROM), random-access memory (RAM), dynamic RAM (DRAM), Double-Data-Rate DRAM (DDRAM), synchronous DRAM (SDRAM), static RAM (SRAM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, polymer memory such as ferroelectric polymer memory, ovonic memory, phase change or ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, or any other type of media suitable for storing information. Each circuit board/socket is typically associated with a pin map, which defines the expected signals to be transmitted on the pins that connect the chip in question to the circuit board. For example, a conventional pin map might assign signal A to pin # 1, signal B to pin # 2, and so on. The chips often have a semiconductor die with signal lines that carry the particular signals, where each signal line is routed within the die to a surface contact such as an electrically conductive bump, and the bumps are bonded to an interface (or “package”). The package routes the signals to various pins according to an order defined by an industry standard socket.
As the product life cycle of a given computer system configuration comes to an end or transitions to a different market segment, it may be replaced by a computer system having circuit boards with one or more different sockets and/or pin maps. The semiconductor dies (and bump configurations) to be plugged into the modified sockets, however, may be the same. Accordingly, each package is typically redesigned to provide the necessary routing between the bumps and pins and is therefore dedicated to a particular pin map.
An example of such an approach is shown in FIG. 1. In the illustrated example, a semiconductor die 10 has a plurality of signal lines 12 (12a–12b) electrically connected to a corresponding plurality of electrically conductive bumps 14 (14a–14b), which are an integral part of the die 10. A semiconductor package 16 is used to route the signals to pins 18 (18a–18b), where the pins 18 connect to a motherboard 20 through a socket 22. It can be seen that depending upon the pin map associated with the socket 22 and/or motherboard 20, the routing within the package 16 can potentially be rather complex. As a result, it is not uncommon for semiconductor packages such as the package 16 to have a multilayer routing configuration, which adds to the cost of the overall package 16. Furthermore, routing signals for relatively long distances can cause impedance mismatching and therefore negatively impact signal integrity. Indeed, it has been determined that the deterioration in signal integrity for certain high speed signals is such that multilayer routing cannot be used. The conventional solution has often been to limit the maximum core frequency of the die in order to minimize the effects of traditional packaging techniques. The result can be a significant decrease in performance.